1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a device and method for reducing cell activation during write operations.
This application claims priority under 35 U.S.C. §119 from Korean Patent Application 10-2006-0107096, filed on Nov. 1, 2006, the contents of which are hereby incorporated by reference in their entirety for all purposes as if fully set forth herein.
2. Description of the Related Art
There are many types of memory devices. Nonvolatile memory types include variable resistive memory devices such as PRAM (Phase change Random Access Memory) containing phase change material, RRAM (Resistive Random Access Memory) containing material having properties of variable resistance, and an MRAM (Magnetic Random Access Memory) containing ferromagnetic material. Materials forming such memory devices have in common a characteristic that a resistance value is varied by current or voltage. In the variable resistive semiconductor memory device, a unit memory cell is constructed of one variable resistance and one switching device. The variable resistance is connected between a bit line and the switching device, and the switching device is generally connected with the variable resistance and a word line. Read and write operations in a variable resistive semiconductor memory device are disclosed in U.S. Pat. Nos. 6,487,113, 6,570,784, and 6,667,900.
One problem with variable resistive semiconductor memory devices and some other memory device types is that activation current demands increase with the number of cells that are activated during a write operation. The problem and a known solution are illustrated in FIGS. 1 and 2, respectively.
FIG. 1 is a flowchart of a write operation according to one example of a conventional art (hereinafter conventional art 1). In write operation S10, all cells of a memory device must be activated in response to a write command. For example, if a write command is associated with a 16 bit data word, then all 16 corresponding cells are activated in a memory device during write operation S10.
FIG. 2 is a flowchart of write operation according to another example of the conventional art (hereinafter conventional art 2). The process illustrated in FIG. 2 seeks to reduce the number of memory cells that must be activated for a write operation. In pre-read step S20, the process reads the current logic state of each target memory cell. Next, in step S21, the process compares each bit of pre-read data from step S20 with each corresponding bit of write data. If all bits match, then the write operation concludes without activating any memory cells. Otherwise, the process advances to steps S22 and S23 where data associated with unmatched bits are selected and written to corresponding memory cells. The process illustrated in FIG. 2 thus reduces the number of cells that must be activated during a write. The reduction is the greatest where all cells match, and can still be substantial where the number of unmatched data bits is relatively small.
The process in FIG. 2 has many disadvantages, however. For example, where all pre-read data bits and write data bits are mismatched, there is no reduction in the number of memory cells that must be activated. Moreover, where there are a large number of mismatched bits, the advantages of conventional art 2 are relatively modest. Devices and methods that further reduce the number of memory cells that must be activated during a write operation are needed.